
module Ram(clock, reset, addr, rw, en1h, data1h, en1l, data1l, en2h, data2h, en2l, data2l);

	// Entradas
	input			clock;
	input			reset;
	input			addr;
	input			rw;
	input			en1h;
	input			en1l;
	input			en2h;
	input			en2l;
	
	// Inouts
	inout			data1h;
	inout			data1l;
	inout			data2h;
	inout			data2l;
	
	// Memória
	reg		[7:0]	Memory	[1023:0];
	
	...

endmodule



